cpldfit: version K.39 Xilinx Inc. Fitter Report Design Name: Main Date: 7-19-2011, 3:19PM Device Used: XC9572XL-10-VQ44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 29 /72 ( 40%) 351 /360 ( 97%) 104/216 ( 48%) 29 /72 ( 40%) 5 /34 ( 15%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 7/18 25/54 88/90 1/ 9 FB2 6/18 29/54 84/90 4/ 9 FB3 8/18 25/54 89/90 0/ 9 FB4 8/18 25/54 90/90* 0/ 7 ----- ----- ----- ----- 29/72 104/216 351/360 5/34 * - Resource is exhausted ** Global Control Resources ** Signal 'iCLK' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 0 0 | I/O : 2 28 Output : 4 4 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 1 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 5 5 ** Power Data ** There are 29 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** INFO:Cpld - Inferring BUFG constraint for signal 'iCLK' based upon the LOC constraint 'P1'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. ************************* Summary of Mapped Logic ************************ ** 4 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State oLED<3> 14 21 FB2_6 31 I/O O STD FAST SET oLED<2> 14 21 FB2_8 32 I/O O STD FAST SET oLED<1> 14 21 FB2_9 33 GSR/I/O O STD FAST SET oLED<0> 14 21 FB2_11 34 GTS/I/O O STD FAST RESET ** 25 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State sr_counter<12> 16 25 FB1_2 STD RESET sr_counter<23> 2 25 FB1_4 STD RESET sr_counter<0> 8 20 FB1_6 STD RESET sr_counter<16> 15 25 FB1_9 STD RESET sr_counter<13> 16 25 FB1_11 STD RESET sr_counter<14> 16 25 FB1_12 STD RESET sr_counter<10> 15 25 FB1_17 STD RESET sr_counter<11> 16 25 FB2_3 STD RESET sr_counter<7> 12 22 FB2_18 STD RESET sr_counter<6> 15 25 FB3_1 STD RESET sr_counter<21> 10 25 FB3_4 STD RESET sr_counter<20> 10 25 FB3_6 STD RESET sr_counter<1> 10 21 FB3_8 STD RESET sr_counter<19> 10 25 FB3_10 STD RESET sr_counter<18> 10 25 FB3_12 STD RESET sr_counter<15> 10 25 FB3_14 STD RESET sr_counter<5> 14 25 FB3_16 STD RESET sr_counter<9> 14 24 FB4_1 STD RESET sr_counter<17> 8 25 FB4_2 STD RESET sr_counter<24> 9 25 FB4_5 STD RESET sr_counter<22> 10 25 FB4_7 STD RESET sr_counter<2> 11 22 FB4_8 STD RESET sr_counter<3> 12 23 FB4_12 STD RESET sr_counter<8> 13 23 FB4_13 STD RESET sr_counter<4> 13 24 FB4_17 STD RESET ** 1 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use iCLK FB1_14 1 GCK/I/O GCK Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 25/29 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/5 0 FB1_1 (b) (b) sr_counter<12> 16 11<- 0 0 FB1_2 39 I/O (b) (unused) 0 0 /\5 0 FB1_3 (b) (b) sr_counter<23> 2 0 /\1 2 FB1_4 (b) (b) (unused) 0 0 \/5 0 FB1_5 40 I/O (b) sr_counter<0> 8 5<- \/2 0 FB1_6 41 I/O (b) (unused) 0 0 \/5 0 FB1_7 (b) (b) (unused) 0 0 \/5 0 FB1_8 42 I/O (b) sr_counter<16> 15 12<- \/2 0 FB1_9 43 GCK/I/O (b) (unused) 0 0 \/5 0 FB1_10 (b) (b) sr_counter<13> 16 11<- 0 0 FB1_11 44 GCK/I/O (b) sr_counter<14> 16 15<- /\4 0 FB1_12 (b) (b) (unused) 0 0 /\5 0 FB1_13 (b) (b) (unused) 0 0 /\5 0 FB1_14 1 GCK/I/O GCK (unused) 0 0 /\5 0 FB1_15 2 I/O (b) (unused) 0 0 \/5 0 FB1_16 (b) (b) sr_counter<10> 15 10<- 0 0 FB1_17 3 I/O (b) (unused) 0 0 /\5 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: sr_counter<0> 10: sr_counter<18> 18: sr_counter<2> 2: sr_counter<10> 11: sr_counter<19> 19: sr_counter<3> 3: sr_counter<11> 12: sr_counter<1> 20: sr_counter<4> 4: sr_counter<12> 13: sr_counter<20> 21: sr_counter<5> 5: sr_counter<13> 14: sr_counter<21> 22: sr_counter<6> 6: sr_counter<14> 15: sr_counter<22> 23: sr_counter<7> 7: sr_counter<15> 16: sr_counter<23> 24: sr_counter<8> 8: sr_counter<16> 17: sr_counter<24> 25: sr_counter<9> 9: sr_counter<17> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs sr_counter<12> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<23> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<0> XXXXXXXXXXX.XXXXX....XXXX............... 20 sr_counter<16> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<13> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<14> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<10> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 29/25 Number of signals used by logic mapping into function block: 29 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/5 0 FB2_1 (b) (b) (unused) 0 0 \/5 0 FB2_2 29 I/O (b) sr_counter<11> 16 13<- \/2 0 FB2_3 (b) (b) (unused) 0 0 \/5 0 FB2_4 (b) (b) (unused) 0 0 \/5 0 FB2_5 30 I/O (b) oLED<3> 14 12<- \/3 0 FB2_6 31 I/O O (unused) 0 0 \/5 0 FB2_7 (b) (b) oLED<2> 14 9<- 0 0 FB2_8 32 I/O O oLED<1> 14 10<- /\1 0 FB2_9 33 GSR/I/O O (unused) 0 0 /\5 0 FB2_10 (b) (b) oLED<0> 14 14<- /\5 0 FB2_11 34 GTS/I/O O (unused) 0 0 /\5 0 FB2_12 (b) (b) (unused) 0 0 /\5 0 FB2_13 (b) (b) (unused) 0 0 /\4 1 FB2_14 36 GTS/I/O (b) (unused) 0 0 0 5 FB2_15 37 I/O (unused) 0 0 \/5 0 FB2_16 (b) (b) (unused) 0 0 \/5 0 FB2_17 38 I/O (b) sr_counter<7> 12 10<- \/3 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: oLED<0> 11: sr_counter<15> 21: sr_counter<24> 2: oLED<1> 12: sr_counter<16> 22: sr_counter<2> 3: oLED<2> 13: sr_counter<17> 23: sr_counter<3> 4: oLED<3> 14: sr_counter<18> 24: sr_counter<4> 5: sr_counter<0> 15: sr_counter<19> 25: sr_counter<5> 6: sr_counter<10> 16: sr_counter<1> 26: sr_counter<6> 7: sr_counter<11> 17: sr_counter<20> 27: sr_counter<7> 8: sr_counter<12> 18: sr_counter<21> 28: sr_counter<8> 9: sr_counter<13> 19: sr_counter<22> 29: sr_counter<9> 10: sr_counter<14> 20: sr_counter<23> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs sr_counter<11> ....XXXXXXXXXXXXXXXXXXXXXXXXX........... 25 oLED<3> ..XX.XXXXXXXXXX.XXXXX....XXXX........... 21 oLED<2> .XX..XXXXXXXXXX.XXXXX....XXXX........... 21 oLED<1> XX...XXXXXXXXXX.XXXXX....XXXX........... 21 oLED<0> X..X.XXXXXXXXXX.XXXXX....XXXX........... 21 sr_counter<7> ....X.XXXXXXXXXXXXXXXXXXXXX............. 22 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 25/29 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use sr_counter<6> 15 10<- 0 0 FB3_1 (b) (b) (unused) 0 0 /\5 0 FB3_2 5 I/O (b) (unused) 0 0 \/5 0 FB3_3 (b) (b) sr_counter<21> 10 5<- 0 0 FB3_4 (b) (b) (unused) 0 0 \/5 0 FB3_5 6 I/O (b) sr_counter<20> 10 5<- 0 0 FB3_6 (b) (b) (unused) 0 0 \/5 0 FB3_7 (b) (b) sr_counter<1> 10 5<- 0 0 FB3_8 7 I/O (b) (unused) 0 0 \/5 0 FB3_9 8 I/O (b) sr_counter<19> 10 5<- 0 0 FB3_10 (b) (b) (unused) 0 0 \/5 0 FB3_11 12 I/O (b) sr_counter<18> 10 5<- 0 0 FB3_12 (b) (b) (unused) 0 0 \/5 0 FB3_13 (b) (b) sr_counter<15> 10 5<- 0 0 FB3_14 13 I/O (b) (unused) 0 0 \/5 0 FB3_15 14 I/O (b) sr_counter<5> 14 9<- 0 0 FB3_16 18 I/O (b) (unused) 0 0 /\4 1 FB3_17 16 I/O (b) (unused) 0 0 \/5 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: sr_counter<0> 10: sr_counter<18> 18: sr_counter<2> 2: sr_counter<10> 11: sr_counter<19> 19: sr_counter<3> 3: sr_counter<11> 12: sr_counter<1> 20: sr_counter<4> 4: sr_counter<12> 13: sr_counter<20> 21: sr_counter<5> 5: sr_counter<13> 14: sr_counter<21> 22: sr_counter<6> 6: sr_counter<14> 15: sr_counter<22> 23: sr_counter<7> 7: sr_counter<15> 16: sr_counter<23> 24: sr_counter<8> 8: sr_counter<16> 17: sr_counter<24> 25: sr_counter<9> 9: sr_counter<17> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs sr_counter<6> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<21> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<20> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<1> XXXXXXXXXXXXXXXXX....XXXX............... 21 sr_counter<19> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<18> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<15> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<5> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 25/29 Number of signals used by logic mapping into function block: 25 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use sr_counter<9> 14 9<- 0 0 FB4_1 (b) (b) sr_counter<17> 8 5<- /\2 0 FB4_2 19 I/O (b) (unused) 0 0 /\5 0 FB4_3 (b) (b) (unused) 0 0 \/5 0 FB4_4 (b) (b) sr_counter<24> 9 5<- \/1 0 FB4_5 20 I/O (b) (unused) 0 0 \/5 0 FB4_6 (b) (b) sr_counter<22> 10 6<- \/1 0 FB4_7 (b) (b) sr_counter<2> 11 6<- 0 0 FB4_8 21 I/O (b) (unused) 0 0 /\5 0 FB4_9 (b) (b) (unused) 0 0 \/5 0 FB4_10 (b) (b) (unused) 0 0 \/5 0 FB4_11 22 I/O (b) sr_counter<3> 12 10<- \/3 0 FB4_12 (b) (b) sr_counter<8> 13 8<- 0 0 FB4_13 (b) (b) (unused) 0 0 /\5 0 FB4_14 23 I/O (b) (unused) 0 0 \/5 0 FB4_15 27 I/O (b) (unused) 0 0 \/5 0 FB4_16 (b) (b) sr_counter<4> 13 10<- \/2 0 FB4_17 28 I/O (b) (unused) 0 0 \/5 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: sr_counter<0> 10: sr_counter<18> 18: sr_counter<2> 2: sr_counter<10> 11: sr_counter<19> 19: sr_counter<3> 3: sr_counter<11> 12: sr_counter<1> 20: sr_counter<4> 4: sr_counter<12> 13: sr_counter<20> 21: sr_counter<5> 5: sr_counter<13> 14: sr_counter<21> 22: sr_counter<6> 6: sr_counter<14> 15: sr_counter<22> 23: sr_counter<7> 7: sr_counter<15> 16: sr_counter<23> 24: sr_counter<8> 8: sr_counter<16> 17: sr_counter<24> 25: sr_counter<9> 9: sr_counter<17> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs sr_counter<9> X.XXXXXXXXXXXXXXXXXXXXXXX............... 24 sr_counter<17> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<24> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<22> XXXXXXXXXXXXXXXXXXXXXXXXX............... 25 sr_counter<2> XXXXXXXXXXXXXXXXXX...XXXX............... 22 sr_counter<3> XXXXXXXXXXXXXXXXXXX..XXXX............... 23 sr_counter<8> X.XXXXXXXXXXXXXXXXXXXXXX................ 23 sr_counter<4> XXXXXXXXXXXXXXXXXXXX.XXXX............... 24 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FTCPE_oLED0: FTCPE port map (oLED(0),EXP23_.EXP,iCLK,'0','0'); FTCPE_oLED1: FTCPE port map (oLED(1),oLED_T(1),iCLK,'0','0'); oLED_T(1) <= ((NOT sr_counter(24)) OR (EXP22_.EXP) OR (NOT sr_counter(18) AND NOT sr_counter(23)) OR (NOT sr_counter(19) AND NOT sr_counter(23)) OR (NOT sr_counter(22) AND NOT sr_counter(23))); FTCPE_oLED2: FTCPE port map (oLED(2),oLED_T(2),iCLK,'0','0'); oLED_T(2) <= ((NOT sr_counter(24)) OR (EXP21_.EXP) OR (sr_led(1).EXP) OR (NOT sr_counter(18) AND NOT sr_counter(23)) OR (NOT sr_counter(19) AND NOT sr_counter(23)) OR (NOT sr_counter(20) AND NOT sr_counter(23)) OR (NOT sr_counter(22) AND NOT sr_counter(23))); FTCPE_oLED3: FTCPE port map (oLED(3),oLED_T(3),iCLK,'0','0'); oLED_T(3) <= ((NOT sr_counter(24)) OR (EXP20_.EXP) OR (NOT sr_counter(22) AND NOT sr_counter(23))); FTCPE_sr_counter0: FTCPE port map (sr_counter(0),sr_counter_T(0),iCLK,'0','0'); sr_counter_T(0) <= ((EXP8_.EXP) OR (NOT sr_counter(0) AND sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(0) AND sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (NOT sr_counter(0) AND sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24))); FDCPE_sr_counter1: FDCPE port map (sr_counter(1),sr_counter_D(1),iCLK,'0','0'); sr_counter_D(1) <= ((EXP31_.EXP) OR (sr_counter(0) AND sr_counter(1)) OR (NOT sr_counter(0) AND NOT sr_counter(1)) OR (sr_counter(23) AND sr_counter(24)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24))); FDCPE_sr_counter2: FDCPE port map (sr_counter(2),sr_counter_D(2),iCLK,'0','0'); sr_counter_D(2) <= ((sr_counter(22).EXP) OR (EXP41_.EXP) OR (NOT sr_counter(0) AND NOT sr_counter(2)) OR (sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(1) AND NOT sr_counter(2)) OR (sr_counter(0) AND sr_counter(1) AND sr_counter(2)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24))); FDCPE_sr_counter3: FDCPE port map (sr_counter(3),sr_counter_D(3),iCLK,'0','0'); sr_counter_D(3) <= ((EXP43_.EXP) OR (NOT sr_counter(0) AND NOT sr_counter(3)) OR (sr_counter(23) AND sr_counter(24))); FDCPE_sr_counter4: FDCPE port map (sr_counter(4),sr_counter_D(4),iCLK,'0','0'); sr_counter_D(4) <= ((EXP46_.EXP) OR (NOT sr_counter(0) AND NOT sr_counter(4)) OR (sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(1) AND NOT sr_counter(4))); FDCPE_sr_counter5: FDCPE port map (sr_counter(5),sr_counter_D(5),iCLK,'0','0'); sr_counter_D(5) <= ((EXP35_.EXP) OR (EXP36_.EXP) OR (NOT sr_counter(0) AND NOT sr_counter(5)) OR (sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(1) AND NOT sr_counter(5)) OR (NOT sr_counter(2) AND NOT sr_counter(5)) OR (NOT sr_counter(3) AND NOT sr_counter(5))); FDCPE_sr_counter6: FDCPE port map (sr_counter(6),sr_counter_D(6),iCLK,'0','0'); sr_counter_D(6) <= ((EXP28_.EXP) OR (EXP37_.EXP) OR (NOT sr_counter(0) AND NOT sr_counter(6)) OR (sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(6) AND NOT sr_counter(1)) OR (NOT sr_counter(6) AND NOT sr_counter(2)) OR (NOT sr_counter(6) AND NOT sr_counter(3))); FDCPE_sr_counter7: FDCPE port map (sr_counter(7),sr_counter_D(7),iCLK,'0','0'); sr_counter_D(7) <= ((EXP27_.EXP) OR (sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(6) AND NOT sr_counter(7))); FDCPE_sr_counter8: FDCPE port map (sr_counter(8),sr_counter_D(8),iCLK,'0','0'); sr_counter_D(8) <= ((sr_counter(3).EXP) OR (EXP44_.EXP) OR (NOT sr_counter(0) AND NOT sr_counter(8)) OR (sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(6) AND NOT sr_counter(8)) OR (NOT sr_counter(7) AND NOT sr_counter(8)) OR (NOT sr_counter(8) AND NOT sr_counter(1))); FDCPE_sr_counter9: FDCPE port map (sr_counter(9),sr_counter_D(9),iCLK,'0','0'); sr_counter_D(9) <= ((sr_counter(17).EXP) OR (EXP47_.EXP) OR (NOT sr_counter(0) AND NOT sr_counter(9)) OR (sr_counter(23) AND sr_counter(24)) OR (NOT sr_counter(6) AND NOT sr_counter(9)) OR (NOT sr_counter(7) AND NOT sr_counter(9)) OR (NOT sr_counter(8) AND NOT sr_counter(9))); FDCPE_sr_counter10: FDCPE port map (sr_counter(10),sr_counter_D(10),iCLK,'0','0'); sr_counter_D(10) <= ((EXP15_.EXP) OR (EXP16_.EXP) OR (NOT sr_counter(10) AND NOT sr_counter(6)) OR (NOT sr_counter(10) AND NOT sr_counter(7)) OR (NOT sr_counter(10) AND NOT sr_counter(8)) OR (NOT sr_counter(10) AND NOT sr_counter(9)) OR (sr_counter(23) AND sr_counter(24))); FTCPE_sr_counter11: FTCPE port map (sr_counter(11),sr_counter_T(11),iCLK,'0','0'); sr_counter_T(11) <= ((EXP18_.EXP) OR (sr_counter(11) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24))); FTCPE_sr_counter12: FTCPE port map (sr_counter(12),sr_counter_T(12),iCLK,'0','0'); sr_counter_T(12) <= ((EXP6_.EXP) OR (EXP7_.EXP) OR (sr_counter(12) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(12) AND sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(12) AND sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(10) AND sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24))); FTCPE_sr_counter13: FTCPE port map (sr_counter(13),sr_counter_T(13),iCLK,'0','0'); sr_counter_T(13) <= ((EXP11_.EXP) OR (sr_counter(14).EXP) OR (sr_counter(13) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(13) AND sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(13) AND sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(10) AND sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24))); FTCPE_sr_counter14: FTCPE port map (sr_counter(14),sr_counter_T(14),iCLK,'0','0'); sr_counter_T(14) <= ((EXP12_.EXP) OR (sr_counter(14) AND sr_counter(23) AND sr_counter(24))); FTCPE_sr_counter15: FTCPE port map (sr_counter(15),sr_counter_T(15),iCLK,'0','0'); sr_counter_T(15) <= ((EXP34_.EXP) OR (sr_counter(15) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(0) AND sr_counter(10) AND sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(6) AND sr_counter(7) AND sr_counter(8) AND sr_counter(9) AND sr_counter(1) AND NOT sr_counter(24) AND sr_counter(2) AND sr_counter(3) AND sr_counter(4) AND sr_counter(5)) OR (sr_counter(0) AND sr_counter(10) AND sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND NOT sr_counter(22) AND NOT sr_counter(23) AND sr_counter(6) AND sr_counter(7) AND sr_counter(8) AND sr_counter(9) AND sr_counter(1) AND sr_counter(2) AND sr_counter(3) AND sr_counter(4) AND sr_counter(5))); FTCPE_sr_counter16: FTCPE port map (sr_counter(16),sr_counter_T(16),iCLK,'0','0'); sr_counter_T(16) <= ((EXP10_.EXP) OR (sr_counter(16) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(16) AND sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24))); FTCPE_sr_counter17: FTCPE port map (sr_counter(17),sr_counter_T(17),iCLK,'0','0'); sr_counter_T(17) <= ((EXP38_.EXP) OR (sr_counter(17) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(0) AND sr_counter(10) AND sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(15) AND sr_counter(16) AND sr_counter(6) AND sr_counter(7) AND sr_counter(8) AND sr_counter(9) AND sr_counter(1) AND NOT sr_counter(24) AND sr_counter(2) AND sr_counter(3) AND sr_counter(4) AND sr_counter(5))); FTCPE_sr_counter18: FTCPE port map (sr_counter(18),sr_counter_T(18),iCLK,'0','0'); sr_counter_T(18) <= ((EXP33_.EXP) OR (sr_counter(18) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(7) AND sr_counter(24))); FTCPE_sr_counter19: FTCPE port map (sr_counter(19),sr_counter_T(19),iCLK,'0','0'); sr_counter_T(19) <= ((EXP32_.EXP) OR (sr_counter(19) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(7) AND sr_counter(24))); FTCPE_sr_counter20: FTCPE port map (sr_counter(20),sr_counter_T(20),iCLK,'0','0'); sr_counter_T(20) <= ((EXP30_.EXP) OR (sr_counter(20) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(7) AND sr_counter(24))); FTCPE_sr_counter21: FTCPE port map (sr_counter(21),sr_counter_T(21),iCLK,'0','0'); sr_counter_T(21) <= ((EXP29_.EXP) OR (sr_counter(21) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(7) AND sr_counter(24))); FTCPE_sr_counter22: FTCPE port map (sr_counter(22),sr_counter_T(22),iCLK,'0','0'); sr_counter_T(22) <= ((EXP40_.EXP) OR (sr_counter(22) AND sr_counter(23) AND sr_counter(24)) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24))); FTCPE_sr_counter23: FTCPE port map (sr_counter(23),sr_counter_T(23),iCLK,'0','0'); sr_counter_T(23) <= ((sr_counter(23) AND sr_counter(24)) OR (sr_counter(0) AND sr_counter(10) AND sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(15) AND sr_counter(16) AND sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(7) AND sr_counter(8) AND sr_counter(9) AND sr_counter(1) AND NOT sr_counter(24) AND sr_counter(2) AND sr_counter(3) AND sr_counter(4) AND sr_counter(5))); FTCPE_sr_counter24: FTCPE port map (sr_counter(24),sr_counter_T(24),iCLK,'0','0'); sr_counter_T(24) <= ((EXP39_.EXP) OR (sr_counter(17) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(15) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(6) AND sr_counter(24)) OR (sr_counter(11) AND sr_counter(12) AND sr_counter(13) AND sr_counter(14) AND sr_counter(16) AND sr_counter(18) AND sr_counter(19) AND sr_counter(20) AND sr_counter(21) AND sr_counter(22) AND sr_counter(7) AND sr_counter(24))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-10-VQ44 -------------------------------- /44 43 42 41 40 39 38 37 36 35 34 \ | 1 33 | | 2 32 | | 3 31 | | 4 30 | | 5 XC9572XL-10-VQ44 29 | | 6 28 | | 7 27 | | 8 26 | | 9 25 | | 10 24 | | 11 23 | \ 12 13 14 15 16 17 18 19 20 21 22 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 iCLK 23 KPR 2 KPR 24 TDO 3 KPR 25 GND 4 GND 26 VCC 5 KPR 27 KPR 6 KPR 28 KPR 7 KPR 29 KPR 8 KPR 30 KPR 9 TDI 31 oLED<3> 10 TMS 32 oLED<2> 11 TCK 33 oLED<1> 12 KPR 34 oLED<0> 13 KPR 35 VCC 14 KPR 36 KPR 15 VCC 37 KPR 16 KPR 38 KPR 17 GND 39 KPR 18 KPR 40 KPR 19 KPR 41 KPR 20 KPR 42 KPR 21 KPR 43 KPR 22 KPR 44 KPR Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-10-VQ44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25